1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and more particularly to a manufacturing method of a cylindrical-capacitor lower electrode for use in semiconductor device.
2. Description of the Related Art
The use of a cylindrical capacitor has been proposed from a necessity to form a capacitor with a required capacitance in a given occupation area that has become very limited, accompanying the reduction of the cell size in a Dynamic Random Access Memory (referred to as DRAM, hereinafter). The cylindrical capacitor has been formed, to date, as follows.
FIG. 2 is a series of cross-sectional views illustrating, in sequence, the steps of a manufacturing method of a cylindrical capacitor according to a first conventional method.
Upon a semiconductor substrate 201, an interlayer insulating film 202 and an etching stopper 204 are formed, and therethrough a conductor plug 203 is formed so as to provide electrical connection with the semiconductor substrate 201, and then a spacer insulating film 205 is formed over the entire surface of the wafer by a known technique of CVD (Chemical Vapour Deposition). Further, by known techniques of photolithography and etching, a hole 206 for a cylindrical capacitor that is to function as a mould of a cylindrical-capacitor lower electrode is formed, and amorphous silicon 207 of which a cylindrical-capacitor lower electrode is to be made in the later step is formed over the entire surface including the internal wall and the bottom of the hole 206 for the cylindrical capacitor (FIG. 2-(a)).
Next, in order to remove the superfluous conductive film other than the one to become the cylindrical-capacitor lower electrode, a coating of an appropriate protective material 208 for etching is applied thick over the entire surface of the wafer so as to fill up the hole 206 for the cylindrical capacitor (FIG. 2-(b)).
Regarding the protective material 208 for etching that can protect the conductive film placed inside of the hole for the cylindrical capacitor when plasma etching of the superfluous part of the conductive film is carried out, there have been examined several materials capable to secure a sufficient etching selection ratio to the conductive film, for example, materials based on silicon oxide film (the organic SOG (Spin-On-Glass), the inorganic SOG, the CVD oxide film and the like, which have excellent filling characteristics) and the photoresists. Among them, the method utilizing the photoresist has attracted the most attention as a method that can be readily realized with a relatively low cost.
Next, carrying out the development, the exposed portion of the photoresist 208 is removed (FIG. 2-(c)).
Next, by means of plasma etching, the superfluous portion of amorphous silicon 207 lying on the wafer surface is removed (FIG. 2-(d)).
Finally, etching is performed over the entire surface by a known method, and thereby a spacer insulating film 205 is removed (FIG. 2-(e)).
In the present example, silicon grains 209 are further formed on the internal and external walls of the cylindrical-capacitor lower electrode, using the hemispherical grain (referred to as HSG, hereinafter) technique.
In the manufacturing method of a cylindrical capacitor, it has become one of the most important things to achieve that the photoresist placed inside of the hole for the cylindrical capacitor is left as much as possible, while the photoresist lying outside of the hole for the cylindrical capacitor is thoroughly removed. The explanation lies in the fact that the positive photoresist remained on the wafer surface may act as a mask and cause unnecessary parts of the conductive film to be left behind when the conductive film is etched, resulting in short-circuit between cylindrical-capacitor lower electrodes and, thus, a lowering of a yield in production. On the other hand, in the case that the amount of the photoresist remaining inside of the hole for the cylindrical capacitor is too small, the part of the conductive film lying on the internal wall of the hole for the cylindrical hole may also receive damage from plasma in the next step of plasma etching over the conductive film.
In order to remove the photoresist lying outside of the hole for the cylindrical capacitor thoroughly, there has been hitherto employed a method in which the dose of exposure is somewhat set at a level of over-exposure at the time of all surface exposure so that the unnecessary part of the photoresist lying on the wafer surface are completely sensitized. The conventional positive photoresist is, however, designed in such a way that the amount of remaining photoresist film after development is rapidly reduced (sensitized), once the dose of exposure exceeds a certain level. This makes suitable control of the dose of exposure difficult. Consequently, when over-exposed, the amount of remaining photoresist film enough to protect the conductive film placed inside of the hole for the cylindrical capacitor may not be secured and there have been occasions when parts of the conductive film lying on the internal wall and the bottom of the hole for the cylindrical capacitor have been also etched at the time of plasma etching over the conductive film.
To solve this problem, a second conventional method is disclosed in Japanese Patent Application Laid-open No.331043/1997. In this method, by lowering the sensitivity of the positive photoresist, the slope of the sensitivity profile showing the relationship between the amount of the remaining photoresist film and the dose of exposure ((the amount of change in film thickness of the photoresist)/(the amount of change in dose of exposure)=.gamma.) is made gentler and the control of the dose of exposure, easier.
The second conventional method is very effective as long as it is used for the purpose of protecting the bottom of the hole for the cylindrical capacitor in plasma etching of the conductive film. However, regarding cost, it is disadvantageous, because the use of the photoresist with a lowered sensitivity requires an additional adjustment for the photoresist used solely in this step.
Further, in order to attain precise control of the dose of exposure in the second conventional method, the photoresist sensitivity must be sufficiently lowered and the exposure time must be set considerably long, which is another drawback in point of throughput.
Moreover, the phenomenon in which, with the normal incidence, the incident light penetrates to the bottom of the hole for the cylindrical capacitor and makes the photoresist recede has not been essentially overcome yet.
In both methods of the first conventional method and the second conventional method, the part of the conductive film which becomes uncovered and shows up above the photoresist, due to the over-exposure, gives rise to several problems in the later steps.
First of all, the part of the internal wall of the hole for the cylindrical capacitor showing above the photoresist is directly exposed to plasma, in plasma etching of the conductive film, and, as a result, the upper end of the hole for the cylindrical capacitor becomes tapered (FIG. 2-(e)). It was found that, because this section is very thin and mechanically fragile, it is easily damaged and broken into particles in the later step of cleaning or the like. In addition, because of its sharply pointed form, a lowering of reliability due to the electric field centralization is very much concerned.
The problem that the conductive film of the upper end of the hole for the cylindrical capacitor takes the shape of a taper becomes very marked when the initial film thickness of the conductive film that is to become the cylindrical-capacitor lower electrode is 80 nm or less.
Meanwhile, one of the techniques to increase the surface area which has come into wide use in recent years is the HSG technique. In this technique, in the region of the transition temperature between amorphous and crystal, amorphous silicon is annealed either in an inert atmosphere or in a high vacuum, and, through the use of the surface migration of silicon atoms, hemispherical or mushroom-shaped grains are formed, with crystal nuclei which have been formed on the surface thereof acting as cores. This technique has attracted much attention in recent years as a method to enlarge the surface area of the electrode.
When an attempt to combine a conventional manufacturing method of a cylindrical capacitor and the HSG technique is made, however, the present inventors discovered that the HSG becomes difficult to be formed on the surface of amorphous silicon, once amorphous silicon is exposed to plasma in plasma etching of the conductive film.
This was found to result from the penetration (knock-on) that the energized dopant ions in plasma makes into the surface of amorphous silicon by a depth of several nim or so, because it inhibits the surface migration of silicon atoms in annealing. The HSG technique is one of the most important techniques in fabrication of the next-generation semiconductor memory device, being effective to increase the capacitance of the capacitor. Therefore, it is considered a great disadvantage in manufacturing the semiconductor memory device with the forthcoming integration degree that the HSG technique cannot be applied to the surface of the capacitor lower electrode.